1. Field of the Invention
The present invention relates to the field of wafer level packaging.
2. Prior Art
Wafer level packaging of micro-electro-mechanical system (MEMS) devices has been an attractive and challenging topic in recent years. A hermetic package can greatly improve the device performance and reliability. Consequently, hermetic bonding is highly preferred in many MEMS devices. Bonding techniques used in the field have included adhesives/polymer/epoxy bond (which are not hermetic bonds), solder eutectic bonds, Si/metal eutectic bonds, metal-metal thermal compression bonds, glass frit bonds, anodic bonds, etc.
A common way of providing electrical lead-outs is through lateral feed-through lines to the edge of the die, which is then sealed by a cap wafer bonded over the die. The feed-through lines crossing the bond rim usually don't allow a metal-related bond. Instead, a dielectric-bond is necessary in this arrangement. However, this lateral lead-out has relatively long feed-through lines, which leads to large parasitic capacitances, cross-talk and substantial interconnection resistances. This technique also precludes any wafer level bumping process.
In order to solve the above-mentioned issues, wafer-level-packages with vertical feed-throughs have been disclosed. Via forming, metal(s) filling and both side metallization are done on a separate single dielectric wafer, such as glass or ceramic. This wafer bonded to a MEMS wafer completes the wafer process, or alternatively, this wafer is just a base material on top of which MEMS devices are built. U.S. Pat. No. 6,384,353 also discloses a method of building a MEMS device on a substrate with filled vias and metallization on both sides, though little processing is described. For reasonably large format wafer processes (e.g., 4-inch or 6-inch above), a wafer with vias calls for substrate rigidity (i.e., wafer thickness) that increases the difficulty/cost of the via process, and also leads to high parasitic coupling capacitances.
In one case, through holes as vertical feed-through paths are firstly formed in a glass wafer. Then the glass wafer is bonded to a MEMS silicon wafer by anodic bonding to form a hermetic package, while the metal pads on the silicon substrate are aligned to the glass vias and thus exposed. The exposed pads allow a further metallization process on the outer surface of the glass wafer to complete the interconnection. Another approach is to fill up the glass vias with metal(s) electro-plated studs and metallization on the glass surface, followed by the anodic bonding to the MEMS wafer to complete the whole process.
Another approach has adopted a combined metallized glass via and lateral feed-through process using glass frit bonding. This process starts the glass wafer with via forming before bonding to another substrate, hence the rigidity of the glass wafer becomes a problem. Normally thin glass of around 150 um thick is used in a small wafer format (e.g., no more than 3-inch), as forming through vias on a thicker wafer will tremendously increase the process difficulty and thus the fabrication cost, and also increases the parasitic capacitances and cross-talk between feed-through paths.
U.S. Pat. No. 6,528,344 discloses another way of forming vertical feed-throughs by use of a cap of silicon. Deep trenches are etched on the silicon cap wafer (only those silicon areas for feed-throughs are not etched), filled with dielectric material, and formed recess of dielectric material for cap gap. After bonding this wafer and the MEMS wafer, contact pads/electrodes of MEMS devices are connected to the silicon islands. Then the cap silicon side of the bonded stack is thinned down to reach or exceed the dielectric materials from the bottom side, so that the silicon islands are exposed and ready for further process to make interconnection. This approach uses silicon as part of the feed-through material and thus a relatively large series resistance is expected. Some of the required process steps, like the dielectric filling, polishing and recessing, and final dielectric membrane releasing, etc., increases the process difficulty and may lead to a stress issue.
In most of the disclosed approaches, vias are solidly filled with metal(s) as feed-through paths. This might cause thermal stress issue due to the large thermal mismatch between substrate and metal(s) and hence device reliability issue.